---
格式版本: 2
标题: "Advance Program (subject to change)"
原文链接: "https://hotchips.org/advance-program/"
发布日期: "2026-09-03"
发布时间校准状态: "found"
发布时间需复核: "否"
发布时间来源: "rule:local:strict_original_body"
发布时间证据: "Published Time: Thu, 03 Sep 2026 15:07:31 GMT"
发布时间校准原因: "规则确认唯一严格发布时间，来源 local:strict_original_body"
发布时间校准置信度: "high"
发布时间候选数量: 4
发布时间严格候选数量: 1
发布时间原页读取状态: "source template page reused from URL open"
发布时间未找到原因: ""
发布时间校准时间: "2026-09-06T00:33:08+08:00"
发布时间仲裁状态: "skipped"
发布时间仲裁尝试次数: 0
发布时间仲裁耗时毫秒: 0
发现时间: "2026-09-06T00:24:40+08:00"
入库时间: "2026-09-05T16:46:04.936Z"
来源平台: "固定入口"
搜索渠道: "fixed_url"
搜索词: "https://hotchips.org/"
匹配关键词:
  - "Marvell"
  - "HBM"
  - "performance"
  - "latency"
  - "bandwidth"
  - "CXL"
  - "GPU"
  - "AI"
相关厂家:
  - "NVIDIA"
  - "AMD"
  - "Meta"
  - "Microsoft"
  - "Google"
  - "OpenAI"
  - "Broadcom"
相关专家:
  []
内容类型: "网页"
抓取工具: "Jina Reader"
清洗工具: "Jina Reader Markdown + Defuddle/Readability 正文提取"
原始附件:
  []
AI优质: "否"
AI打分: 39
AI分档: "非优质"
AI质检状态: "不通过"
AI打分理由: "正文为Hot Chips 2026 advance program会议节目单，仅列出演讲标题、演讲者与时间，无架构、规格、客户、量产或部署等实质技术事实，属于导航/摘要壳页面。来源为会议官网，虽权威但仅为议程；相对知识库已有Rubin等产品信息，本页只增加标题级预告，无新增可核验事实。命中‘正文不可用’类否决：标题与正文错配、正文仅为其他文章/演讲导航，完整性0—2且最高54分，不能依据标题补全。"
AI质检模型: "zj-deepseek-v4-flash"
AI质检时间: "2026-09-06T00:58:48+08:00"
AI主题相关性: 12
AI来源权威性: 12
AI新颖性: 10
AI技术细节: 3
AI商业部署信号: 1
AI完整性: 1
AI评分提示词版本: "v17-精简生产版"
AI评分提示词SHA256: "48fb9777f386026761b4873eaff30807694fb11e9b352d7c69bf2dfde750cc7d"
AI评分知识库版本: "knowledge_base_v1-20260819+runtime.92"
AI评分知识库SHA256: "60a2554e31d747e68f935f2311b8b8b5d75eff191eaf73eceffba8e80cfd0753"
AI评分知识库检索词: "[\"Hot Chips\",\"https://hotchips.org/\",\"Rubin\",\"HBM\",\"rack-scale\",\"CXL\",\"RAS\",\"GPU\",\"NVIDIA\",\"Google\",\"Meta\",\"Microsoft\"]"
AI评分知识库命中: "[{\"id\":\"july-correct-0033\",\"title\":\"Microsoft, Alphabet, Meta Pivot from Buy to Build in AI\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"Rubin\",\"RAS\",\"GPU\",\"NVIDIA\",\"Google\",\"Meta\",\"Microsoft\"],\"rank\":-17.094780712675746},{\"id\":\"runtime-613d1ef67a8028d2dc2916c4\",\"title\":\"Nvidia, MediaTek Bring Custom Chips to AI Racks\",\"sourceType\":\"ai_excellent_article\",\"time\":\"2026-08-31\",\"matchedTerms\":[\"HBM\",\"rack-scale\",\"RAS\",\"GPU\",\"NVIDIA\",\"Google\",\"Microsoft\"],\"rank\":-14.53790495000697},{\"id\":\"july-correct-0020\",\"title\":\"NVIDIA Vera Rubin：引領代理 AI 的時代\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"Rubin\",\"HBM\",\"RAS\",\"GPU\",\"NVIDIA\",\"Meta\"],\"rank\":-14.357545241182208},{\"id\":\"runtime-e8b946c3131877fe7add476b\",\"title\":\"COMPUTE Peeling Apart That Supposed $120 Billion Chip Deal Google Inked With Marvell August 27, 2026\",\"sourceType\":\"ai_excellent_article\",\"time\":\"2026-08-27\",\"matchedTerms\":[\"Hot Chips\",\"CXL\",\"RAS\",\"GPU\",\"Google\",\"Meta\"],\"rank\":-14.071652395797578},{\"id\":\"july-correct-0104\",\"title\":\"NVIDIA Vera Rubin 提升每瓦性能，为全球合作伙伴实现最低 Token 成本\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"Rubin\",\"RAS\",\"GPU\",\"NVIDIA\",\"Google\",\"Microsoft\"],\"rank\":-13.796219044624344}]"
采集批次: "2026年9月6日0点22分52秒"
采集批次ID: "20260906-002252-51243ba9"
去重键: "https://hotchips.org/advance-program"
---

Title: Advance Program (subject to change)

URL Source: https://hotchips.org/advance-program/

Published Time: Thu, 03 Sep 2026 15:07:31 GMT

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# Advance Program (subject to change)

## Tutorials: Sunday, August 23rd, 2026[Permalink](https://hotchips.org/advance-program/#tutorials "Permalink")

| Time (PDT) | Title | Presenters |
| --- | --- | --- |
| 8:00AM-9:00AM | _Breakfast/registration_ |  |
| 9:00AM-11:00AM | _Tutorial 1: Memory technology_ Chair: Suresh Rajgopal |  |
|  | **Memory: Feeding AI’s voracious hunger for data** | Jim Handy, Objective Analysis |
|  | **Evolving memory architectures for AI** | Raghu Sreeramaneni, Micron |
|  | **HBM Base Die: How HBM Will Evolve Using Advanced Logic Processes** | Sangwook Han, Samsung |
|  | **Advanced packaging for High Bandwidth Memory (HBM)** | Jaesik Lee, SK Hynix |
| 11:00AM-11:30AM | _Break_ |  |
| 11:30AM-12:30PM | _Tutorial 1: Memory technology (cont)_ |  |
|  | **3D DRAM based Accelerator for Generative Inference** | Sudeep Bhoja (D-Matrix) & Aayush Ankit (Meta) |
|  | **HBF in AI Compute - A System Architect’s view** | Anurag Agrawal (Oxmiq Labs) & Radhakrishna Giduthuri (PRAXMATI) |
| 12:30PM-1:45PM | _Lunch_ |  |
| 1:45PM-3:15PM | _Tutorial 2: RISC-V_ Chair: Marcel Tromp |  |
|  | **Update on RISC-V standards and adoption, including profiles and platforms** | Krste Asanovic, SiFive |
|  | **Evolution of enterprise open-source on RISC-V and architectural convergence on RVA23** | Gordan Markus, Canonical |
| 3:15PM-3:45PM | _Break_ |  |
| 3:45PM-5:00PM | _Tutorial 2: RISC-V (cont)_ |  |
|  | **RISC-V profile and platform for interoperability with NVIDIA GPUs** | Frans Sijstermans, NVIDIA |
|  | **RISC-V for automotive: opportunities and challenges** | Thomas Roecker, Infineon |
| 5:00PM-7:00PM | _Reception_ |  |

## Conference Day 1: Monday, August 24th, 2026[Permalink](https://hotchips.org/advance-program/#conference-day1 "Permalink")

| Time (PDT) | Title | Presenters |
| --- | --- | --- |
| 8:00AM-9:15AM | _Breakfast/registration_ |  |
| 9:15AM-9:30AM | _Welcome_ |  |
| 9:30AM-11:00AM | _Session: CPU 1_ Chair: Ian Bratt |  |
|  | **The future IBM Z & LinuxONE Processor and AI Inference Acceleration Chipset** | Christian Zoellin, IBM |
|  | **Intel Core Series 3, codename Wildcat Lake** | Lance Hacking, Intel |
|  | **NVIDIA’s Vera CPU** | Jonathon Evans & Polychronis Xekalakis, NVIDIA |
| 11:00AM-11:30AM | _Break_ |  |
| 11:30AM-1:00PM | _Session: CPU 2_ Chair: Gabriel Southern |  |
|  | **Next-Generation Arm-based CPU FUJITSU-MONAKA for green AI data center** | Ryohei Okazaki, Fujitsu |
|  | **Arm AGI : A Disaggregated, Chiplet-Based Server SoC for scalable coherency and memory Bandwidth in the Terabyte/s Era** | Saurabh Pradhan & Deepak Goel, Arm |
|  | **Diamond Rapids: Next Generation Intel Xeon CPU** | Akhilesh Kumar & Krishnakanth Sistla, Intel |
| 1:00PM-2:15PM | _Lunch_ |  |
| 2:15PM-3:15PM | _Keynote_ Chair: Cliff Young |  |
|  | **Compute in Motion: Challenges of Autonomous Driving** | Daniel Rosenband, Waymo |
| 3:15PM-4:15PM | _Session: Automotive_ Chair: Yasuo Ishii |  |
|  | **Eagle-N: Chiplet-Based SoC for Scalable Automotive AI** | KM Lim, BOS Semiconductors |
|  | **Waymo sensor fusion processor** | Sabareesh Ravikumar & Pieter Kapsenberg, Waymo |
| 4:15PM-4:45PM | _Break_ |  |
| 4:45PM-6:45PM | _Session: GPU_ Chair: Pradeep Dubey |  |
|  | **NVIDIA Rubin GPU: Driving the Era of Agentic AI** | Manas Mandal, Rajballav Dash & Rouslan Dimitrov, NVIDIA |
|  | **AMD Instinct MI400 Series GPU Architecture** | Alan Smith & Maiyuran Subramaniam, AMD |
|  | **System Architecture of the AMD MI400 Series GPU** | Steve Scott, David Riddoch & Krishna Doddapaneni, AMD |
|  | **Crescent Island: GPU Designed for Agentic AI Inference** | Sumit Mohan & Hong Jiang, Intel |
| 6:45PM-7:00PM | _TCMM Awards_ |  |
|  | **TCMM Awards** | Gabriel Southern |
| 7:00PM-9:00PM | _Reception_ |  |

## Conference Day 2: Tuesday, August 25th, 2026[Permalink](https://hotchips.org/advance-program/#conference-day2 "Permalink")

| Time (PDT) | Title | Presenters |
| --- | --- | --- |
| 8:00AM-8:45AM | _Breakfast/registration_ |  |
| 8:45AM-9:45AM | _Session: FPGA_ Chair: Thierry Tambe |  |
|  | **Secure Computing SoC for Physical AI, Data Center, and Mission Critical Systems** | Jaideep Dastidar & Thomas To, AMD |
|  | **Versal RF** | Jeff Cuppett, AMD |
| 9:45AM-10:45AM | _Session: Memory_ Chair: Jae W. Lee |  |
|  | **Samsung LPDDR5X-PIM: World’s First LPDDR based Processing in Memory (PIM) Solution for AI Inference** | Karam Hwang, Samsung |
|  | **XCENA MX1 CXL Computational Memory Device** | Harry Kim (XCENA) & Jinin So (Samsung Electronics) |
| 10:45AM-11:15AM | _Break_ |  |
| 11:15AM-12:45PM | _Session: Networking & Interconnect_ Chair: Greg Papadopoulos |  |
|  | **Thor Ultra: An Ethernet NIC Chip Optimized for AI & HPC** | Hemal Shah, Broadcom |
|  | **NVIDIA BlueField-4 Processor Powers the AI Factory Operating System** | Idan Burstein, NVIDIA |
|  | **NVIDIA Spectrum-X Multiplane Network Architecture** | Gilad Shainer, NVIDIA |
| 12:45PM-2:15PM | _Lunch_ |  |
| 2:15PM-4:15PM | _Session: AI 1_ Chair: Sherry Xu & John Wright |  |
|  | **Meta’s Custom AI Silicon: From Recommendation to Dual-Mandate with GenAI** | Srinagesh Loke, Cindy Chen & Jatinder Singh, Meta |
|  | **Think Fast: LPU Accelerator for Heterogeneous Compute** | Igor Arsovski & Santosh Raghavan, NVIDIA |
|  | **The Cerebras Rack-Scale Architecture for Wafer Scale Engine** | Jean-Philippe (J.P.) Fricker, Cerebras |
|  | **MAIA 200: A Data Center Scale AI system - MAIA-200 Accelerator** | Prashant Ranjan & Jackson Peng, Microsoft |
| 4:15PM-4:45PM | _Break_ |  |
| 4:45PM-6:15PM | _Session: AI 2_ Chair: Brucek Khailany |  |
|  | **Dataflow at Scale: the SN50 RDU** | Raghu Prabhakar, SambaNova |
|  | **The Eighth Generation TPU Family: Two Chips Optimized for Training and Serving in the Agentic Era** | Norman Jouppi & Sridhar Lakshmanamurthy, Google |
|  | **You Can Just Build ~~Things~~ … Chips** | Richard Ho, Ravi Narayanaswami & Chris Leary, OpenAI |
| 6:15PM-6:20PM | _Vice-Chair closing remarks_ |  |
|  | **Vice-Chair closing remarks** | Nhon Quach |

## Posters[Permalink](https://hotchips.org/advance-program/#posters "Permalink")

| Title | Authors & Affiliation |
| --- | --- |
| Croc: Training the Next Generation Chip Designers on Domain-Specific End-to-End Open Source Silicon | Enrico Zelioli, Philippe Sauter, Thomas Benz, Hannah Pochert, Luisa Wüthrich, Beat Muheim, Frank Kagan Gürkaynak, and Luca Benini; ETH Zurich |
| Gemmelos: A Dual-Chip Platform in Intel 16 for Multimodal Edge AI Applications | Nicolas Rakela, Yash Kodali, Marie-Anne Xu, Alonso Zul Alonso, John Lomax, Jonathan Wang, Ethan Gao, Jasmine Angle, Sunjin Choi, Borivoje Nikolić, and Vikram Jain; UC Berkeley |
| Pistil: A 16-nm Accelerator Co-Designed with a 20-Chiplet 2.5D System-in-Package Architecture for Distributed Small Language Model Inference at the Edge | Nestor Cuevas _, Matthew Adiletta_, Haebin Do, Yun-Chen Lo, Kevin Kim, Jennifer Zhou, Kevin He, Alicia Golden, Isaac Leffler, Connor Ryan, Chris Green, Garrett Tan, Alexandra Forsythe, Nichole Murray, Lee Kimes, Rick Stevens, David Brooks, and Gu-Yeon Wei; Harvard, Lockheed Martin |
| Tensor Processing with Large-scale Homodyne Photonic Crossbar | Lian Zhou, Yuan Li, Yun-Jhu Lee, Chun-Ho Lee, Kaiwen Xue, Kiwon Kwon, Weipeng Zhang, Songlin Zhao, Jason Moraes, Ryan Hamerly, Mengjie Yu, and Zaijun Chen; Opticore |
| From Python to Silicon: First Tapeouts Produced by an End-to-End Open-Source Hardware Compiler | Ankur Limaye, Nicolas Bohm Agostini, David Kong, Nrusinga Charan Gantayat, Gianmarco Accordi, Max Ramstad, Lakshmi Varshika Mirtinti, Vito Giovanni Castellana, Joseph Manzano, Jeff Jun Zhang, Gage Hills, and Antonino Tumeo; PNNL |
| ETHEREAL: a 17µs-latency event-driven GNN processor for high-resolution edge-AI vision | Adrian Kneip, Martin Lefebvre, Victoria Catalán Pastor, Daniel Gehrig, Davide Scaramuzza, Marian Verhelst, and Charlotte Frenkel; KU Leuven, TU Delft |
| LUTs and Bolts: eFPGA SoC with Hardened MVM Engine for Deep Learning in 28nm | Jason Cheung, Caroline Locke, Andrew Park, Surya Thenarasu, Larry Tang, James Hoe, Prashanth Mohan, and Ken Mai; CMU |
| HiVec: Scalable and Energy Efficient CGRA in a RISC-V SoC for Wearables | Rakshith Harish, Rohan Juneja, Pranav Dangi, Zhenyu Bai, Vishnu Nambiar, Yi Sheng Chong, Bin Zhao, Vishruti Ranjan, Rahul Dutta, Li-Shiuan Peh, Tulika Mitra, and Anh Tuan DO; A*STAR and National University of Singapore |
| CN101 - Thermodynamic Computing for Generative AI in Digital CMOS | Brandon Birchall, Lars Holdijk, Denis Melanson, Vincent Cheung, Nicholas Lehrter, Maxwell Aifer, Samuel Duffield, Jan Ernst, Saavan Patel, Antonio J. Martinez, Gavin Crooks, Patrick J. Coles, Zach Belateche, and Marc Bright; Normal Computing |
| From Microarchitecture to Silicon: An End-to-End RISC-V CPU Design Course | Junichiro Kadomoto, Tomoya Ota, Riki Onaga, Yuichi Matsuno, and Makoto Ikeda; University of Tokyo |
| A Low-Power and Real-Time Vision-Language Navigation Processor with 3D Spatial Reasoning for Embodied Agents | Seryeong Kim, Jongjun Park, Sangmyoung Lee, Hyungnam Joo, Wonhoon Park, Seokchan Song, Junha Ryu, Gwangtae Park, Sangjin Kim, Jiwon Choi, Seongyon Hong, Hyeonrae Kim, and Hoi-Jun Yoo; KAIST |

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