--- 格式版本: 2 标题: "Hot Chips: OpenAI Jalapeno Presentation" 原文链接: "https://taekim.substack.com/p/hot-chips-openai-jalapeno-presentation" 发布日期: "2026-09-01" 发布时间校准状态: "found" 发布时间需复核: "否" 发布时间来源: "llm:scrape:original_script_field" 发布时间证据: "datePublished: 2026-09-01T04:16:29+00:00" 发布时间校准原因: "datePublished明确标注文章发布时间，优先采用；会议日期为正文事件时间，不采用。" 发布时间校准置信度: "1" 发布时间候选数量: 16 发布时间严格候选数量: 2 发布时间原页读取状态: "source template page reused from URL open" 发布时间未找到原因: "" 发布时间校准时间: "2026-09-02T02:25:24+08:00" 发布时间仲裁状态: "confirmed" 发布时间仲裁尝试次数: 1 发布时间仲裁耗时毫秒: 4914 发现时间: "2026-09-02T02:24:29+08:00" 入库时间: "2026-09-01T18:27:19.273Z" 来源平台: "Substack 数据中心相关博客搜索" 搜索渠道: "source_template" 搜索词: "site:substack.com Hot Chips" 匹配关键词: - "Scale-up" - "HBM" - "SRAM" - "roadmap" - "performance" - "latency" - "throughput" - "AI" 相关厂家: - "OpenAI" - "NVIDIA" - "Google" - "Broadcom" - "Celestica" 相关专家: [] 内容类型: "网页" 抓取工具: "Free Fetch + Defuddle" 清洗工具: "Defuddle Markdown + Defuddle/Readability 正文提取" 原始附件: [] AI优质: "是" AI打分: 78 AI分档: "高置信优质" AI质检状态: "通过" AI打分理由: "OpenAI自研Jalapeno芯片在Hot Chips首次公开，含内存切片架构、200G scale-up以太网、1.7GHz频率、9个月RTL完成等具体技术细节，并披露Broadcom/Celestica合作与多代路线图，对AI加速器…" AI质检模型: "zj-deepseek-v4-flash" AI质检时间: "2026-09-02T02:27:32+08:00" AI主题相关性: 16 AI来源权威性: 9 AI新颖性: 19 AI技术细节: 17 AI商业部署信号: 9 AI完整性: 8 AI摘要: "OpenAI在Hot Chips大会发布自研LLM推理芯片Jalapeno，9个月完成RTL设计，采用内存切片架构，可实现单用户近1500 tokens/s的吞吐并显著降低延迟。" AI摘要模型: "ali-deepseek-v4-flash" AI摘要时间: "2026-09-01T23:06:38.443Z" 采集批次: "2026年9月1日23点56分52秒" 采集批次ID: "20260901-235652-761" 去重键: "https://taekim.substack.com/p/hot-chips-openai-jalapeno-presentation" --- *Presenters: Richard Ho, VP of Hardware. Ravi Narayanaswami, Member of Technical Staff. Chris Leary, Member of Technical Staff. Presented at the Hot Chips conference on Tuesday, August 25, 2026.* Here are the most important distilled parts of the presentation. I manually chose and pulled the quotes: Richard leads the hardware team at OpenAI. He was part of Google’s TPU team. Ravi spent a decade at Cruise and also worked at Google. Chris was a Google TPU software lead. **First speaker: Richard** “The jalapeno chip. It is here. It’s real. We have the systems in the lab.” “This chip basically allows OpenAI to do **full stack optimization from the models through the software and compiler all the way down into the silicon**.” “We did basically **the entire RTL execution in nine months**.” They were able to do it so quickly because they started with a blank slate with a new design with no legacy architecture or legacy chips to support. They focused on accelerating OpenAI workloads. Since those workloads were large language models, all LLMs benefited. **Second speaker: Ravi** “Just two things that matter. How long the user waits and how much energy the request takes.” *OSS performance* “Almost 1500 tokens per second per user. This used to be the domain of SRAM-based accelerators. Well, **HBM is not the bottleneck**. On the right, we delivered today’s highest throughput at 4x less latency.” The world needs fast and cheap. Jalapeno delivers both. *DeepSeek performance* “700 tokens per second per user. Clearly SRAM based territory. 5x lower latency for today’s highest throughput. So it’s the same story. Only difference is the advantages grew. The larger the model, the larger the advantage.” *Kimi performance* “We didn’t spend much time optimizing Kimi at all, I think we spent a few days” *Design Philosophy* “We needed to decide when we starting off the project whether we want to make a heavily decode, hyper optimized chip or **a chip that was really good at decode but it was really good at pre-fill as well. And we chose the latter**.. Another reason we decided we wanted a single chip solution was preserving locality.” **Third speaker: Chris** “The show FLOPS don’t matter. It’s how many flops you actually deliver in the workload to the user.” “And that leads us to the Jalapeno architecture. It is **a memory-sliced architecture.” “Every core has a local view of its own HBM slice.”** “That means there's no contention on some global memory subsystem, but it also means that **you have to think about how your workload is going to map onto this machine**.” Jalapeno was designed to reduce wait times by placing data where it is needed and having it arrive when it is needed. The architecture minimizes chip idle time and data movement, keeping data close to the compute. It is optimized for LLM inference. “What we've built is actually a **specialized collective network for the cores to talk to each other at high performance**. Again, you have to plan out how you're going to map onto the machine. **But the benefit of this is it's choreographed and orchestrated to have those values in the registers exactly when you need them.**” **The Team** “Okay, **so you want to build the best chip in the world, and you want to go real fast. You have two choices. Build a really big team or build a really small team. We picked the latter**, and we actually kind of discovered over the course of this program what makes that work well. And what we discovered was really the key to that really fast cadence that you saw at the beginning of the talk, was being able to run this loop. You might call it agile, you might call it co-design.” The team introduced a new hardware programming environment, which OpenAI’s AI models became super proficient at writing programs. “But **with modern frontier LLMs like Sol and Astra, it is really good at writing kernels for this spatial architecture**.” “Even for ones that we've expert tuned, often the AI is able to **squeeze some additional performance** out.” “The whole idea is that we want to unlock the ability to really get them for the workloads and deliver the performance and performance per watt. Because at the end of the day, that’s the **only thing that matters in terms of end-to-end workloads is how we get that delivered performance per watt**.” **Back to Richard:** “This is step one of a multi-generational roadmap. We have **generation two already well under development, and we’re heading towards tapeout in some of the number of months**... The whole point is that this is going to lower the cost of infrastructure, as I said at the beginning. And I’m really proud of the team.” “ **I also want to give a really big shout out to our partners, Broadcom and Celestica**, who are very key partners for us to be able to deliver this capability here.” **Q&A** Question: For the nine-month tape out number how much of the chip was existing Broadcom IP versus what you designed from scratch, right? Answer: **Most of the chip is designed from scratch**. The compute die I think only has like some interface IP and there’s an IO chip as well as you saw in the diagram a lot of the interfaces are existing IP, the rest of it was all like fresh RTL in XLS plus and Verilog. Question: Michael with NVIDIA. Curious if you could elaborate a little bit about your networking setup. So specifically, do you use ESUN for scale-up networking protocol or something custom? And are the links using 200 gigabit or 100 gig? Answer: We’re using a **scale-up Ethernet protocol and it’s 200 gigabit**. Thanks. Question: Did you have any specialized cells, specialized memories, any specialized circuit and silicon techniques that you used? Answer: That was **standard cell methodology**. Question: What frequency were you targeting? Answer: So we’re running 1.7 gigahertz on the parts that we have in the lab, but the POR we should get up to 1.8. So it’s sandbagged a little bit. And it is sustained performance. — Tae: If you want to know what OpenAI’s chip means for investors, read my Hot Chips conference [key takeaways post](https://taekim.substack.com/p/hot-chips-conference-initial-5-takeaways) from last week.