--- 格式版本: 2 标题: "AMD brings UCIe connectivity to Versal adaptive chips" 原文链接: "https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/" 发布日期: "2026-08-27" 发布时间校准状态: "found" 发布时间需复核: "否" 发布时间来源: "llm:local:strict_original_body" 发布时间证据: "Published Time: Thu, 27 Aug 2026 08:41:38 GMT" 发布时间校准原因: "正文明确标注Published Time，为文章真实发布时间，优先级最高。" 发布时间校准置信度: "1" 发布时间候选数量: 44 发布时间严格候选数量: 15 发布时间原页读取状态: "source template page reused from URL open" 发布时间未找到原因: "" 发布时间校准时间: "2026-08-27T17:57:33+08:00" 发布时间仲裁状态: "confirmed" 发布时间仲裁尝试次数: 1 发布时间仲裁耗时毫秒: 90447 发现时间: "2026-08-27T17:55:40+08:00" 入库时间: "2026-08-27T09:59:33.917Z" 来源平台: "SDxCentral 搜索" 搜索渠道: "source_template" 搜索词: "site:sdxcentral.com AMD" 匹配关键词: - "Scale-up" - "NVLink" - "bandwidth" - "AI" 相关厂家: - "AMD" - "NVIDIA" - "Meta" - "Microsoft" 相关专家: [] 内容类型: "网页" 抓取工具: "Jina Reader" 清洗工具: "Jina Reader Markdown + Defuddle/Readability 正文提取" 原始附件: [] 图片摘要: - "✓ ./assets/img-ca27c130.png | other | " - "✓ ./assets/img-94dbe40e.png | other | " - "✓ ./assets/img-2e5fec02.webp | other | " - "✓ ./assets/img-5eed4ad6.jpg | other | " - "✓ ./assets/img-6750588c.jpg | other | " - "✓ ./assets/img-cccae6a1.webp | other | " - "✓ ./assets/img-1d9365d7.jpg | other | " - "✓ ./assets/img-c976427e.jpg | other | " - "✓ ./assets/img-bca435ad.webp | other | " - "✓ ./assets/img-e408dc8f.webp | other | " AI优质: "否" AI打分: 54 AI分档: "非优质" AI质检状态: "不通过" AI打分理由: "正文主线是AMD为Versal RF自适应芯片加入UCIe 1.1连接，而非机架级AI基础设施。SDxCentral属专业媒体但并非官方原文。相较固定知识库，新增事实包括Versal RF率先支持UCIe、最高80 TOPS DSP算力、封装内聚合带宽可达数Tbps及生产芯粒预计于2027年第四季度可用；正文也提供了后续SoC扩展路线。尽管信息完整且具备新产品路线和量产时间信号，但应用重点是异构芯粒与RF系统，未说明其进入AI机架、规模部署或改变机架拓扑，命中弱相关强否决，最高54分。" AI质检模型: "gpt-5.6-sol" AI质检时间: "2026-08-27T17:59:45+08:00" AI主题相关性: 4 AI来源权威性: 11 AI新颖性: 14 AI技术细节: 11 AI商业部署信号: 5 AI完整性: 9 AI评分提示词版本: "v17-精简生产版" AI评分提示词SHA256: "48fb9777f386026761b4873eaff30807694fb11e9b352d7c69bf2dfde750cc7d" AI评分知识库版本: "knowledge_base_v1-20260819+runtime.9" AI评分知识库SHA256: "249b1d8a63b21728ee756645a5e0bd7ab90b585c0f21053f5284375f1623f126" AI评分知识库检索词: "[\"AMD\",\"site:sdxcentral.com AMD\",\"NVLink\",\"RAS\",\"NVIDIA\",\"Meta\",\"Microsoft\",\"UCIe\",\"URL\",\"GMT\",\"LDN\",\"www.xceleratedcompute.com/london/2026\"]" AI评分知识库命中: "[{\"id\":\"runtime-5095d81c147567ab9111181d\",\"title\":\"Meta’s custom transport protocol embraces packet chaos to boost AI throughput\",\"sourceType\":\"ai_excellent_article\",\"time\":\"\",\"matchedTerms\":[\"AMD\",\"RAS\",\"Meta\",\"URL\",\"LDN\",\"www.xceleratedcompute.com/london/2026\"],\"rank\":-16.2654530964397},{\"id\":\"runtime-f25234b5fb900c12eebcf43a\",\"title\":\"Scale-in? Nvidia’s ‘fifth’ pillar of AI networking rests on shaky ground\",\"sourceType\":\"ai_excellent_article\",\"time\":\"\",\"matchedTerms\":[\"NVLink\",\"RAS\",\"NVIDIA\",\"URL\",\"GMT\",\"LDN\",\"www.xceleratedcompute.com/london/2026\"],\"rank\":-15.02540162946273},{\"id\":\"july-correct-0027\",\"title\":\"Microsoft Taps AMD For At Scale AI CPU And GPU Clusters\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"AMD\",\"NVLink\",\"NVIDIA\",\"Meta\",\"Microsoft\"],\"rank\":-13.721067487702545},{\"id\":\"july-correct-0033\",\"title\":\"Microsoft, Alphabet, Meta Pivot from Buy to Build in AI\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"AMD\",\"RAS\",\"NVIDIA\",\"Meta\",\"Microsoft\",\"URL\"],\"rank\":-13.633381335367346},{\"id\":\"july-correct-0015\",\"title\":\"AMD to join the optical interconnect party with 2027 Instinct GPUs\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"AMD\",\"NVIDIA\",\"Meta\",\"Microsoft\",\"URL\"],\"rank\":-12.894784393853193}]" AI摘要: "AMD为Versal自适应可编程芯片新增UCIe小芯片互连支持，使其可搭配独立共封装小芯片，而非必须集成在单体裸片上。首批支持面向RF产品，提供最高80 TOPS DSP算力及多Tbps级封装内带宽，生产芯片预计2027年第四季度上市。" AI摘要模型: "ali-deepseek-v4-flash" AI摘要时间: "2026-08-27T18:59:52.323Z" 采集批次: "2026年8月27日17点55分15秒" 采集批次ID: "20260827-175515-082" 去重键: "https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips" --- Title: AMD brings UCIe connectivity to Versal adaptive chips URL Source: https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/ Published Time: Thu, 27 Aug 2026 08:41:38 GMT Markdown Content: # * Channels * [The AI Channel](https://www.sdxcentral.com/ai/) * [The Networking Channel](https://www.sdxcentral.com/network-sdn/) * [The Cybersecurity Channel](https://www.sdxcentral.com/security/) * [The Distributed Infrastructure Channel](https://www.sdxcentral.com/distributed-infrastructure/) * [The Telecom Channel](https://www.sdxcentral.com/telecom-nfv/) * [The Silicon & Supercomputing Channel](https://www.sdxcentral.com/storage-silicon/) * [The Cloud & Storage Channel](https://www.sdxcentral.com/cloud/) * Media * [News](https://www.sdxcentral.com/news/) * [Analysis](https://www.sdxcentral.com/analysis/) * [Editors' Views](https://www.sdxcentral.com/control-plane/) * [Industry Views](https://www.sdxcentral.com/opinions/) * [Video Interviews](https://www.sdxcentral.com/video-interviews/) * [Broadcasts](https://www.sdxcentral.com/broadcasts/) * [On Demand Broadcasts](https://www.sdxcentral.com/broadcasts/past/) * [Explainers](https://www.sdxcentral.com/sdx-explainers/) * [MarketWatch](https://www.sdxcentral.com/marketwatch/) * [Press Releases](https://www.sdxcentral.com/press-releases/) * [Resources](https://www.sdxcentral.com/resources/) * Live Events * Xcelerated Compute Series * [The Xcelerated Compute Show | LDN 2026](https://www.xceleratedcompute.com/london/2026/) * [The Xcelerated Compute Show | MEX 2026](https://www.xceleratedcompute.com/cancun/2026/) * [The Xcelerated Compute Show | NYC 2027](https://www.xceleratedcompute.com/new-york/2027/) * Digital Infrastructure Series * [Yotta 2026](https://www.yotta-event.com/) * [](https://www.sdxcentral.com/sdx-en/account/login/?next=%2Fnews%2Famd-brings-ucie-connectivity-to-versal-adaptive-chips%2F) * [](https://www.sdxcentral.com/sdx-en/search/) Search * Show Menu * Channels * Back * [The AI Channel](https://www.sdxcentral.com/ai/) * [The Networking Channel](https://www.sdxcentral.com/network-sdn/) * [The Cybersecurity Channel](https://www.sdxcentral.com/security/) * [The Distributed Infrastructure Channel](https://www.sdxcentral.com/distributed-infrastructure/) * [The Telecom Channel](https://www.sdxcentral.com/telecom-nfv/) * [The Silicon & Supercomputing Channel](https://www.sdxcentral.com/storage-silicon/) * [The Cloud & Storage Channel](https://www.sdxcentral.com/cloud/) * Media * Back * [News](https://www.sdxcentral.com/news/) * [Analysis](https://www.sdxcentral.com/analysis/) * [Editors' Views](https://www.sdxcentral.com/control-plane/) * [Industry Views](https://www.sdxcentral.com/opinions/) * [Video Interviews](https://www.sdxcentral.com/video-interviews/) * [Broadcasts](https://www.sdxcentral.com/broadcasts/) * [On Demand Broadcasts](https://www.sdxcentral.com/broadcasts/past/) * [Explainers](https://www.sdxcentral.com/sdx-explainers/) * [MarketWatch](https://www.sdxcentral.com/marketwatch/) * [Press Releases](https://www.sdxcentral.com/press-releases/) * [Resources](https://www.sdxcentral.com/resources/) * Live Events * Back * Xcelerated Compute Series * [The Xcelerated Compute Show | LDN 2026](https://www.xceleratedcompute.com/london/2026/) * [The Xcelerated Compute Show | MEX 2026](https://www.xceleratedcompute.com/cancun/2026/) * [The Xcelerated Compute Show | NYC 2027](https://www.xceleratedcompute.com/new-york/2027/) * Digital Infrastructure Series * [Yotta 2026](https://www.yotta-event.com/) Close modal ## Search Suggestions [Get the Report: How leading storage architects are solving the AI memory crunch](https://www.sdxcentral.com/resources/the-storage-supplement/) * [Home](https://www.sdxcentral.com/) * [News](https://www.sdxcentral.com/news/) * [The Silicon & Supercomputing Channel](https://www.sdxcentral.com/storage-silicon/) # AMD brings UCIe connectivity to Versal adaptive chips Chip giant embraces open chiplet interconnect standards to unlock heterogeneous compute August 26, 2026 By[Ben Wodecki](https://www.sdxcentral.com/profile/ben-wodecki/)[Have your say](https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/#comments) [](https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/)[](https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/)[](https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/)[](https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/)[](https://www.sdxcentral.com/news/amd-brings-ucie-connectivity-to-versal-adaptive-chips/)[](https://www.addtoany.com/share) ![Image 3: AMD Versal graphic](./assets/img-94dbe40e.png) – AMD AMD is adding universal chiplet interconnect express (UCIe) support to its Versal line of adaptive programmable chips. Versal chips are a modern successor to the Xilinx field-programmable gate arrays following AMD’s [acquisition back in 2022](https://www.amd.com/en/newsroom/press-releases/2022-2-14-amd-completes-acquisition-of-xilinx.html). They replace monolithic single-use hardware with a chiplet-based reconfigurable system that can be wired for a specific task or workload ranging from AI acceleration to radio frequency (RF) processing. [](https://media.datacenterdynamics.com/media/images/bec0f83f-4cb9-42c1-8e24-8a96703724f0.original.png)![Image 4: AMD graphic outlining potential applications for its UCIe-supporting Versal SoCs](./assets/img-2e5fec02.webp) – AMD This latest update sees AMD add UCIe connectivity, allowing the ability to pair them with separate co-packaged chiplets via UCIe rather than requiring everything built into one monolithic die. The open standard interconnect provides up to multiterabit-per-second aggregate in-package bandwidth, AMD claims. The chip giant is initially extending support for its RF Versal products with plans to further add system-on-a-chip (SoC) options “as the market matures.” Production chiplets are expected to be available in the fourth quarter of 2027. Kirk Saban, corporate VP for product, software, and solutions in AMD’s embedded business, explained in a statement that specialized chiplet designs are driving a new era of innovation in the semiconductor space. “AMD Versal RF Series chiplets are uniquely positioned to be the starting point to harness UCIe connectivity, bringing heterogeneous compute architecture with up to 80 trillion operations per second (TOPS) of digital signal processing (DSP) compute, integrated RF converters, and SWaP-C (size, weight, power, and cost) benefits to customers and unlocking the next generation of adaptive RF systems,” the exec added. AMD joined Microsoft, Meta, and Qualcomm in co-developing UCIe specifications in 2022. While its Versal SoCs will feature UCIe 1.1 connectivity, [version 2.0](https://www.synopsys.com/blogs/chip-design/ucie-2-0-setting-the-tone-for-chiplet-interoperability.html) of the specification was released in August 2024, supporting 3D packaging to boost bandwidth density and power efficiency. UCIe is also being used to provide the bridge in [NVLink Fusion](https://www.sdxcentral.com/news/nvidia-launches-nvlink-fusion-to-connect-custom-cpus-and-asics-with-nvidia-hardware/), the Nvidia scale-up-centric backplane allowing non-Nvidia accelerators to intertwine with its hardware. Ayar Labs is among the companies [signed up to NVLink Fusion](https://www.sdxcentral.com/news/ayar-labs-joins-nvlink-fusion-bringing-co-packaged-optics-to-nvidias-ai-infrastructure/) and claimed to be the first vendor to launch an [optical interconnect chiplet built with UCIe](https://www.sdxcentral.com/news/ayar-labs-unveils-worlds-first-ucie-optical-chiplet/) last April.