---
格式版本: 2
标题: "NVIDIA NVLink Fusion Brings NVHBM to Next-Generation AI Infrastructure"
原文链接: "https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure/"
发布日期: "2026-08-26"
发布时间校准状态: "found"
发布时间需复核: "否"
发布时间来源: "rule:configured_publication_date_rule"
发布时间证据: "nvidia-dev-blog-search-publication-date html:original: Aug 26, 2026"
发布时间校准原因: "信源发布日期识别规则直接确认发布时间"
发布时间校准置信度: "high"
发布时间候选数量: 1
发布时间严格候选数量: 1
发布时间原页读取状态: "source template page reused from URL open"
发布时间未找到原因: ""
发布时间校准时间: "2026-08-27T19:54:26+08:00"
发布时间仲裁状态: "skipped"
发布时间仲裁尝试次数: 0
发布时间仲裁耗时毫秒: 0
发现时间: "2026-08-27T19:51:40+08:00"
入库时间: "2026-08-27T11:54:34.277Z"
来源平台: "NVIDIA Developer Blog 搜索"
搜索渠道: "source_template"
搜索词: "https://developer.nvidia.com/search?q=HBM&page=1&filters=techblogs"
匹配关键词:
  - "HBM"
  - "NVLink"
  - "bandwidth"
  - "AI"
  - "XPU"
  - "Scale-up"
  - "NVL72"
  - "SRAM"
  - "delivery"
  - "deployment"
  - "performance"
  - "latency"
  - "throughput"
相关厂家:
  - "NVIDIA"
相关专家:
  []
内容类型: "网页"
抓取工具: "Free Fetch + Defuddle"
清洗工具: "Defuddle Markdown + Defuddle/Readability 正文提取"
原始附件:
  []
图片摘要:
  - "★ ./assets/img-4e250d6c.webp | diagram | 并排对比图：NVLink Fusion XPU搭配NVHBM与标准HBM的XPU，展示NVHBM窄接口节省中央die面积，用于更多计算单元。"
AI优质: "是"
AI打分: 85
AI分档: "高置信优质"
AI质检状态: "通过"
AI打分理由: "正文主线是NVLink Fusion与NVHBM支撑定制XPU接入机架级AI基础设施，属于NVIDIA官方一手技术说明。相较固定知识库中的Rubin、NVL72及其他机架系统材料，本文新增NVHBM定制基底芯片、内存控制器移入3D HBM堆栈及定制PHY等架构事实，并披露相对HBM4e最高30%带宽提升、15%功耗下降、67% PHY与支持区缩减、30%主计算裸片空间增加，以及NVLink Fusion chiplet、NVLink-C2C和机架级统一域机制。技术规格完整且可核验，命中新架构/关键部件与生产级深技术通道；但未披露具名客户、订单、量产时间或明确可用日期，商业部署信号较弱，正文也缺少原始发布日期。"
AI质检模型: "gpt-5.6-sol"
AI质检时间: "2026-08-27T19:54:50+08:00"
AI主题相关性: 20
AI来源权威性: 15
AI新颖性: 18
AI技术细节: 20
AI商业部署信号: 3
AI完整性: 9
AI评分提示词版本: "v17-精简生产版"
AI评分提示词SHA256: "48fb9777f386026761b4873eaff30807694fb11e9b352d7c69bf2dfde750cc7d"
AI评分知识库版本: "knowledge_base_v1-20260819+runtime.7"
AI评分知识库SHA256: "2d08daa800e4aaf8f32428770a398a6fddb773ec6de396decbc9d7689bcb65f7"
AI评分知识库检索词: "[\"NVIDIA\",\"HBM\",\"NVLink\",\"bandwidth\",\"NVL72\",\"HBM4\",\"rack-scale\",\"rack scale\",\"RAS\",\"GPU\",\"XPU\",\"Intel\"]"
AI评分知识库命中: "[{\"id\":\"july-correct-0095\",\"title\":\"Inside NVIDIA Rubin GPU Architecture: Powering the Era of Agentic AI\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"NVIDIA\",\"HBM\",\"NVLink\",\"bandwidth\",\"NVL72\",\"HBM4\",\"rack-scale\",\"rack scale\",\"RAS\",\"GPU\",\"Intel\"],\"rank\":-21.586115232767543},{\"id\":\"july-correct-0079\",\"title\":\"AAI 2026: AMD Launches AMD Helios Rackscale Solution for Frontier AI\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"NVIDIA\",\"HBM\",\"bandwidth\",\"NVL72\",\"HBM4\",\"rack-scale\",\"RAS\",\"GPU\",\"Intel\"],\"rank\":-18.358826094963955},{\"id\":\"july-correct-0089\",\"title\":\"Setting a World Record for MoE Pre-Training on NVIDIA GB300 NVL72\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"NVIDIA\",\"HBM\",\"NVLink\",\"bandwidth\",\"NVL72\",\"rack-scale\",\"RAS\",\"GPU\"],\"rank\":-17.317885298086107},{\"id\":\"historical-jan-apr-02\",\"title\":\"二、Google Cloud Next '26：AI Hypercomputer 与第八代 TPU 发布\",\"sourceType\":\"curated_item\",\"time\":\"2026-01_to_2026-04\",\"matchedTerms\":[\"NVIDIA\",\"bandwidth\",\"NVL72\",\"rack-scale\",\"GPU\",\"Intel\"],\"rank\":-17.120487429353442},{\"id\":\"july-correct-0034\",\"title\":\"AMD Fires Back at Nvidia with Helios AI System, Epyc CPUs\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"NVIDIA\",\"bandwidth\",\"NVL72\",\"rack-scale\",\"RAS\",\"GPU\",\"Intel\"],\"rank\":-15.239802576754942}]"
AI摘要: "NVIDIA发布NVLink Fusion与NVHBM技术，帮助超大规模和AI原生企业将自研XPU和CPU接入NVIDIA AI基础设施，简化定制AI加速器从设计到机架级部署的流程。"
AI摘要模型: "ali-deepseek-v4-flash"
AI摘要时间: "2026-08-27T18:59:51.333Z"
采集批次: "2026年8月27日19点35分18秒"
采集批次ID: "20260827-193518-269"
去重键: "https://developer.nvidia.com/blog/nvidia-nvlink-fusion-brings-nvhbm-to-next-generation-ai-infrastructure"
---

AI factories must support increasingly large models and more complex reasoning [workloads](http://workloads.to/). To keep up with the insatiable compute demands of AI workloads, hyperscalers and AI-native companies are developing custom AI accelerators, or XPUs. Deploying these accelerators at scale requires high-bandwidth memory (HBM) to keep compute fed, sufficient package and silicon area for more compute, efficient power delivery, and a resilient supply chain. It also requires a rack-scale architecture for deploying XPUs into data center infrastructure.

[NVIDIA NVLink Fusion](https://www.nvidia.com/en-us/data-center/nvlink-fusion/) is the connective technology and IP that enables hyperscalers and AI natives to deploy custom XPUs and CPUs into the NVIDIA AI infrastructure platform. They can use the NVIDIA scale-up and scale-out technology stack, ecosystem, and MGX rack-scale architecture to reduce development and deployment complexity, improve performance, and accelerate time to market for semi-custom AI factories.

At the package level, NVHBM, complements this unified architecture. NVHBM is a custom HBM base-die technology designed and validated with leading memory vendors that enables increased memory bandwidth, better area savings, and lower power consumption. These improvements can help custom XPUs support larger models, read KV cache data faster, and improve training and large-scale inference.

## Why bandwidth, die area, and power drive accelerator design

Training, inference, and agentic AI workloads increasingly depend on high-throughput access to model weights, KV cache, and activation data. As AI systems scale from individual accelerators to rack-level compute domains, the accelerator package must balance compute logic, power delivery, thermal design, and high-bandwidth memory.

HBM places vital memory bandwidth close to the accelerator, but qualifying leading memory technology, package integration, and validation can become a bottleneck for custom accelerator programs. Through NVLink Fusion, customers gain access to NVHBM base dies that are validated with leading memory manufacturers, helping reduce integration and qualification bottlenecks.

| **Feature** | NVHBM **benefit** |
| --- | --- |
| **Bandwidth** | Up to 30% more memory bandwidth compared with standard HBM4e |
| **Area** | More efficient interface connections allow up to 25% more compute die area for additional XPU capabilities |
| **Power** | Up to 15% lower HBM power usage compared with standard HBM4e adds up savings across thousands of XPUs |

*Table 1.**NVHBM brings three main platform-level advantages to AI accelerator programs: higher memory bandwidth, more package and silicon area, and lower HBM power usage*

## The memory bandwidth bottleneck in modern AI accelerators

AI accelerator performance depends on how consistently compute engines are supplied with data. Higher HBM speeds increase usable memory bandwidth within a given package budget, improving the ability to serve bandwidth-intensive phases of training and inference. NVHBM delivers up to **30% more memory bandwidth per stack** compared with standard HBM4e. For memory-bound or partially memory-bound AI workloads, that translates into better accelerator utilization and higher throughput. This can increase per-user token throughput during large-model inference by moving data between HBM and compute cores faster, keeping them fed.

While NVHBM increases memory bandwidth within each accelerator, NVLink Fusion connects accelerators across larger domains so workloads can use distributed compute and memory more efficiently.

This scale-up domain is especially critical when using advanced routing techniques like [expert parallelism (EP) or WideEP](https://developer.nvidia.com/blog/scaling-large-moe-models-with-wide-expert-parallelism-on-nvl72-rack-scale-systems/). In these scenarios, different experts reside on different GPUs and require seamless, high-speed synchronization across the entire rack. [NVIDIA NVLink](https://www.nvidia.com/en-us/data-center/nvlink/), the scale-up networking fabric for AI factories, transfers activations and hidden states between experts and helps synchronize distributed caches across the scale-up fabric. NVHBM minimizes data starvation by keeping the local compute engines consistently fed.

## More package area, more flexibility

For custom AI silicon, every square millimeter matters. Accelerator designers must decide how much area to allocate to matrix engines, vector units, on-chip SRAM, cache hierarchy, control logic, memory interfaces, network-on-chip, and scale-up connectivity. A custom memory implementation can help reduce the design and package overhead associated with accessing HBM, freeing up area for workload-specific capabilities.

As AI workloads diversify, this additional die area gives hyperscalers more flexibility to optimize XPUs for inference serving, recommendation systems, multimodal pipelines, or internal training workloads. By reducing the area required for the memory interface, NVHBM enables teams to dedicate more of the chip directly to performance.

Area savings are achieved primarily through a redesigned physical memory interface (PHY). Standard HBM relies on wider interface connections, increasing the total package footprint. NVHBM uses a custom base die optimized for efficiency, featuring reduced I/O area requirements achieved by moving the memory controller into the 3D HBM stack and integrating a custom PHY.

Compared with the JEDEC HBM4e standard, this design reduces PHY and support area by up to 67%. The narrower interface also simplifies interposer routing, providing up to 80% more usable silicon across the entire layout.

![Side-by-side diagram comparing an NVIDIA NVLink Fusion XPU with NVHBM and a custom XPU with standard HBM. NVHBM’s narrower interface leaves more central die area for XPU features.](./assets/img-4e250d6c.webp)

Figure 1. Comparison of die area savings with NVHBM compared to standard HBM

As shown in Figure 1, shrinking the memory interface connections enables the central AI compute die to expand into the newly freed space. This reclamation provides up to a 30% increase in available main-die silicon for compute or other features. The additional silicon area enables XPU designers toadd more capabilities within a fixed package footprint.

## Power savings for efficient scaling

Power is one of the hardest constraints in modern AI infrastructure. HBM power contributes to the accelerator power budget, package thermal design, rack power envelope, and data center cooling plan. NVHBM enables **15% lower HBM power usage** compared to standard HBM4e, creating additional power and thermal headroom for compute.

Power savings matter at multiple levels. At the XPU level, lower HBM power can improve performance per watt and create room for more compute or higher sustained utilization. At the rack level, it can help reduce pressure on power delivery and cooling systems. At AI factory scale, even modest reductions in memory subsystem power can add up across thousands of accelerators. When compounded across an entire **1-gigawatt** **data center** using 2,000W XPUs, power savings can enable up to **15,000** **additional XPUs** in compute headroom.

The benefit is especially important for large-model inference. XPUs must repeatedly read model weights and KV-cache data while serving users at low latency and high throughput. Reducing the energy spent moving that data can help support faster inference on large models, larger batch sizes, and more efficient use of deployed power.

## Combining NVLink Fusion with NVHBM at rack scale

NVHBM boosts XPU performance and efficiency at the chip level. NVLink Fusion enables hyperscalers and AI natives to connect their XPUs to the rest of the NVIDIA AI platform. By compounding a 30% increase in memory bandwidth, 25% more die area, and 15% HBM power savings, these co-designed architectural improvements translate into a significant 30% overall end-to-end performance increase per XPU.

This connectivity is achieved through the NVLink Fusion chiplet, which bridges custom XPUs and the NVLink fabric, connecting all XPUs in a rack into a single scale-up domain. Now in its sixth generation, NVLink is the only proven, purpose-built scale-up networking fabric for AI factories, delivering leading performance and intelligent resiliency. Upstream, the XPUs can connect to the CPUs via NVLink-C2C.

NVLink Fusion adopters can combine custom XPUs and CPUs with NVIDIA scale-up and scale-out technology stack and ecosystem to reduce development and deployment complexity, increase performance, and accelerate time to market for semi-custom AI factories. And by standardizing on a single unified architecture, NVLink Fusion simplifies operations across the data center, enables flexible reprovisioning of data center capacity, and enables custom AI XPUs to integrate with GPUs for heterogeneous compute.

## The next phase of custom AI silicon

NVLink Fusion provides a common scale-up foundation for GPUs, custom XPUs and CPUs, networking, and rack-level software. NVHBM complements that foundation with greater memory performance, compute density, HBM power efficiency, and supply resiliency for next-generation accelerators. These technologies give partners a more direct path from custom AI accelerator design to rack-scale deployment and production volume.

Learn more about [NVLink Fusion](https://www.nvidia.com/en-us/data-center/nvlink-fusion/) and [industry adoption of NVHBM](https://blogs.nvidia.com/blog/nvlink-fusion-nvhbm-custom-high-bandwidth-memory).

![Side-by-side diagram comparing an NVIDIA NVLink Fusion XPU with NVHBM and a custom XPU with standard HBM. NVHBM’s narrower interface leaves more central die area for XPU features.](./assets/img-4e250d6c.webp)