--- 格式版本: 2 标题: "SK Hynix banks on optical interconnects to defend its HBM crown" 原文链接: "https://www.sdxcentral.com/news/sk-hynix-banks-on-optical-interconnects-to-defend-its-hbm-crown/" 发布日期: "2026-08-21" 发布时间校准状态: "found" 发布时间需复核: "否" 发布时间来源: "llm:local:strict_original_body" 发布时间证据: "August 21, 2026 ByBen WodeckiHave your say" 发布时间校准原因: "标题下方明确标注发布时间August 21, 2026，符合标题附近明确标注的发布时间优先级，优先于其他元数据。" 发布时间校准置信度: "1" 发布时间候选数量: 39 发布时间严格候选数量: 14 发布时间原页读取状态: "source template page reused from URL open" 发布时间未找到原因: "" 发布时间校准时间: "2026-08-29T10:40:19+08:00" 发布时间仲裁状态: "confirmed" 发布时间仲裁尝试次数: 2 发布时间仲裁耗时毫秒: 17911 发现时间: "2026-08-29T10:39:31+08:00" 入库时间: "2026-08-29T02:40:56.767Z" 来源平台: "SDxCentral 搜索" 搜索渠道: "source_template" 搜索词: "site:sdxcentral.com Switch tray" 匹配关键词: - "HBM" - "performance" - "AI" - "CPO" - "latency" - "bandwidth" 相关厂家: - "NVIDIA" - "Meta" 相关专家: [] 内容类型: "网页" 抓取工具: "Jina Reader" 清洗工具: "Jina Reader Markdown + Defuddle/Readability 正文提取" 原始附件: [] AI优质: "否" AI打分: 54 AI分档: "非优质" AI质检状态: "不通过" AI打分理由: "正文主线是SK海力士与高校研究者提出以CPO、光子中介层连接处理器和共享内存池的光学中心架构，属于专业媒体对原始论文的完整报道。固定知识库未见该光学内存接口方案的同事件记录，新增事实是将光互连延伸至内存接口的架构设想；但未披露带宽、延迟、功耗等量化指标，也无真实平台实测、产品发布、量产、客户或部署时间表。命中“学术方案缺少生产平台和真实端到端指标”强否决项，最高54分。" AI质检模型: "gpt-5.6-sol" AI质检时间: "2026-08-29T10:41:07+08:00" AI主题相关性: 14 AI来源权威性: 10 AI新颖性: 11 AI技术细节: 10 AI商业部署信号: 1 AI完整性: 8 AI评分提示词版本: "v17-精简生产版" AI评分提示词SHA256: "48fb9777f386026761b4873eaff30807694fb11e9b352d7c69bf2dfde750cc7d" AI评分知识库版本: "knowledge_base_v1-20260819+runtime.52" AI评分知识库SHA256: "aad70953f4eb6c68e7a16456d17d0917b0bedbe3b757d1a0d5bef7d145345575" AI评分知识库检索词: "[\"HBM\",\"performance\",\"Switch tray\",\"site:sdxcentral.com Switch tray\",\"CPO\",\"Compute Tray\",\"RAS\",\"NVIDIA\",\"Meta\",\"SK\",\"URL\",\"GMT\"]" AI评分知识库命中: "[{\"id\":\"runtime-bfe02a4bdf19930993595f4a\",\"title\":\"SK Hynix, Sandisk unveil first standard for high-bandwidth flash\",\"sourceType\":\"ai_excellent_article\",\"time\":\"2026-08-04\",\"matchedTerms\":[\"HBM\",\"performance\",\"RAS\",\"Meta\",\"SK\",\"URL\"],\"rank\":-15.843563731961495},{\"id\":\"july-correct-0071\",\"title\":\"SK Group and NVIDIA Expand Strategic Partnership Across AI Factories and Next-Generation Memory\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"HBM\",\"RAS\",\"NVIDIA\",\"SK\",\"URL\"],\"rank\":-15.579866930874775},{\"id\":\"july-correct-0017\",\"title\":\"AMD challenges Nvidia’s networking dominance with Helios racks boasting 50% higher bandwidth\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"HBM\",\"performance\",\"Switch tray\",\"RAS\",\"NVIDIA\",\"SK\",\"URL\"],\"rank\":-11.952099186250058},{\"id\":\"runtime-5b8a3335997f3b1b31558541\",\"title\":\"STORE You Probably Forget How Cheap Memory Used To Be – And Is Not So Now\",\"sourceType\":\"ai_excellent_article\",\"time\":\"2026-08-25\",\"matchedTerms\":[\"HBM\",\"RAS\",\"NVIDIA\",\"Meta\",\"SK\"],\"rank\":-10.752718465283504},{\"id\":\"july-correct-0020\",\"title\":\"NVIDIA Vera Rubin：引領代理 AI 的時代\",\"sourceType\":\"labeled_article\",\"time\":\"2026-07\",\"matchedTerms\":[\"HBM\",\"RAS\",\"NVIDIA\",\"Meta\"],\"rank\":-9.493384434613267}]" AI摘要: "SK海力士与多所高校研究人员联合发布论文，主张以光互连和共封装光学（CPO）取代铜互连，提出“以光为中心的架构”，通过光子中介层将内存池与AI加速器直接相连，以突破内存墙。" AI摘要模型: "ali-deepseek-v4-flash" AI摘要时间: "2026-09-07T02:08:20.712Z" 采集批次: "2026年8月29日10点39分17秒" 采集批次ID: "20260829-103917-332" 去重键: "https://www.sdxcentral.com/news/sk-hynix-banks-on-optical-interconnects-to-defend-its-hbm-crown" --- Title: SK Hynix banks on optical interconnects to defend its HBM crown URL Source: https://www.sdxcentral.com/news/sk-hynix-banks-on-optical-interconnects-to-defend-its-hbm-crown/ Published Time: Sat, 29 Aug 2026 01:44:08 GMT Markdown Content: This website uses cookies to ensure you get the best experience on our website. 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A [paper](https://www.nature.com/articles/s41928-026-01681-6) penned by the South Korean memory giant along with academic researchers from institutions including the University of Virginia, Nanyang Technological University, and the Massachusetts Institute of Technology (MIT) examined how optical compute interconnects could support next-generation AI systems. The researchers back replacing copper interconnects with optical links as “the most promising path toward future scalability.” CPO technologies are increasingly gaining traction as a means to speed up chip-to-chip links inside compute trays and between switches. But SK Hynix and its research partners view CPO as a means to extend interconnects all the way to the memory interface. [](https://media.datacenterdynamics.com/media/images/SKHaINigSeu_CPO_GiSulNonMun_SoGae_eng_03.original.jpg)![Image 4: SK Hynix's optics-centric architecture](./assets/img-276fa59a.jpg) – SK Hynix The paper describes an “optics-centric architecture” in which photonic interposers – a chip-packaging substrate that routes data using both electrical signals and light – could be employed to directly connect memory pools and processors in order to maximize the efficiency of data movement across a computing system. The idea could allow multiple AI accelerators to share large memory pools at vastly higher speeds than conventional storage links, allowing system-level data movement to flow efficiently at scale. “Extending optical interconnects to the memory interface would overcome the physical constraints surrounding compute chips, removing limitations on both memory capacity and the number of electrical connections,” University of Virginia Professor Kyusang Lee explained. “It would also allow multiple AI accelerators to share a large memory pool, which would make AI infrastructure far more adaptable as AI models continue to grow in scale.” The ongoing memory shortage, which has resulted in skyrocketing hardware prices, largely stems from AI data center builders. While accelerators have exponentially improved performance levels in recent years, high-bandwidth memory (HBM) lags as it consumes far more silicon wafer capacity per gigabit compared to conventional memory hardware, creating sizable performance bottlenecks. That’s resulted in AI infrastructure operators snapping up all available supply to meet the demands of their high–performance stacks. Means to smash through the memory wall have seen development of faster, lower-power alternatives like [2T0C](https://www.sdxcentral.com/news/researchers-build-zero-charge-chip-to-topple-the-ai-memory-wall/) from South Korea’s Electronics and Telecommunications Research Institute or [chiplet-based interconnects](https://www.sdxcentral.com/news/credo-spearheading-ocp-project-to-develop-open-chiplet-interconnects/) to provide low-latency connectivity between compute engines and memory. Even SK Hynix is [throwing its weight behind a potential HBM alternative](https://www.sdxcentral.com/news/sk-hynix-sandisk-unveil-first-standard-for-high-bandwidth-flash/) in the form of the Sandisk-developed [high-bandwidth flash](https://www.sdxcentral.com/analysis/beyond-hbm-the-flash-memory-technology-that-could-reshape-ai-infrastructure/). But given its place as a market leader in HBM, SK Hynix’s backing of CPO acts as a strategic defense mechanism to keep its prized product relevant. After all, the frenzy for HBM propelled the South Korean memory giant’s market valuation to [eclipse $1 trillion](https://www.sdxcentral.com/news/ram-raid-profit-frenzy-sees-micron-sk-hynix-hit-1t-market-caps/) and fuel the [largest ever market launch by a foreign firm](https://www.sdxcentral.com/news/sk-hynix-raises-265bn-in-blockbuster-us-ipo/) on the Nasdaq. ![Image 5: SK hynix HBM 'chips'](./assets/img-e1b5a79b.jpg) 15 Jul 2026 # [SK Hynix rollercoaster sees stock surges at home and abroad](https://www.sdxcentral.com/news/sk-hynix-rollercoaster-sees-stock-surges-at-home-and-abroad/) South Korean chip giant jumps almost 30% on Nasdaq and 13% on KRX “As customers continue to build larger AI systems, the importance of optical interconnects will only increase,” Seunghoon Hong, AI infra team lead at SK Hynix, noted. “Memory companies are evolving beyond the role of supplying individual components to becoming partners that help strengthen the competitiveness of customers’ entire systems through technologies such as CPO.” “Going forward, we will continue to expand open collaboration with customers and ecosystem partners to accelerate innovation across the AI infrastructure landscape,” Hong added. More widely, some of the industry’s top interconnect players have joined forces to develop [open specifications for CPO](https://www.sdxcentral.com/news/industry-giants-unite-to-define-open-co-packaged-optics-for-next-gen-ai-infrastructure/) in AI infrastructure. Nvidia, meanwhile, is set to be among the first players to launch CPO network switches in its upcoming [Spectrum-6 line](https://www.sdxcentral.com/news/nvidia-debuts-spectrum-6-switches-to-power-next-gen-ai-networking/) – with neocloud darling Lambda providing a sneak peek into the [InfiniBand-based switch](https://www.sdxcentral.com/news/lambda-offers-glimpse-into-nvidias-cpo-switch-enabling-more-tokens-through-substantial-power-savings/) earlier this year. Stay ahead of the latest networking channel trends. Subscribe to SDxCentral. [Create an Account to Subscribe Now](https://www.sdxcentral.com/create-your-free-sdx-central-account-today/)