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标题: "Developing AI-Native Automated Virtual Chiplet Eco-systems: Shift Left, Shift Up, and Shift Out to accelerate Chiplet adoption » Open Compute Project"
原文链接: "https://www.opencompute.org/blog/developing-ai-native-automated-virtual-chiplet-eco-systems-shift-left-shift-up-and-shift-out-to-accelerate-chiplet-adoption"
发布日期: "2026-07-28"
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发布时间证据: "7/28/2026 · Posted by Raghu Shankar"
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发现时间: "2026-08-10T16:24:29+08:00"
入库时间: "2026-08-10T08:27:13.367Z"
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AI优质: "否"
AI打分: 35
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去重键: "https://www.opencompute.org/blog/developing-ai-native-automated-virtual-chiplet-eco-systems-shift-left-shift-up-and-shift-out-to-accelerate-chiplet-adoption"
---

**Key Takeaways:**

- SIPs with 2.5D and 3D chiplets deliver 10x functionality, modular dies, higher yields, lower cost, and cross-generation reusability.
- Chiplet adoption needs clear value proposition, demand sizing, and vendor profitability proof to justify supply-side investments across products and generations.
- Shift left: Move evaluation to planning and design space exploration for early PPAC estimates, lowering risk, cost, and time to decision.
- Shift up: Focus at the architecture layer, abstract physical and protocol details, use HLS synthesis, simulation, emulation, and prototyping.
- Shift out: Expand pool of buyers and sellers to maximize explorations.
- Develop AI native virtual ecosystem: Automate chiplet interop testing with virtual prototyping.

**Attend** the panel session on this topic at [OCP Global Summit](https://www.opencompute.org/summit/global-summit) as part of Server - Open Chiplet Economy track on October 15, 2026 in San Jose, CA.

Talk 9060 — “AI-native Virtual Chiplet Eco-systems with industry best practices to accelerate Chiplet adoption”, Raghu Shankar (Entrepreneur), Matt Holdrege (Microchip), Marc Meunier (ARM), Nandan Nayampally (Baya Systems), and Lichen Weng (Tenstorrent).

![](https://146a55aca6f00848c565-a7635525d40ac1c70300198708936b4e.ssl.cf1.rackcdn.com/images/c78d597a2e9546598f1962e552faa2159089715d.jpg)

### Chiplet adoption challenge

Systems-in-package (SIPs) with 2.5D and 3D heterogeneous integration, consisting of multiple dies and chiplets deliver 10x more functionality than traditional monolithic chips. This capability enables innovative solutions for diverse needs in scientific computing, automotive, edge computing, and aerospace/defense.

Chiplets deliver modular building blocks with smaller dies at higher yields thereby lowering costs. It also enables higher reusability across product lines and across generations. This approach has been adopted by established vendors, on proven legacy designs, in well-understood markets, and in closed eco-systems of few vendors. Beyond that, dies and chiplets can be available from a wide range of organizations and generations. Many technologies and standards are in place to speed interoperability and adoption in multi-vendor eco-systems.

Despite the advantages of SIPs and chiplets, broad adoption across a wider range of market opportunities with lower volumes and at lower budgets remains a major challenge. There is a **bottleneck** right up-front during planning and design phases to identify promising ventures.

- First, the market need must be clearly defined, including the value proposition, solution adoption potential, price sensitivity, and demand profile.
- Second, each vendor across the supply chain must be confident that their investment will be profitable at a level of manageable risk. Further each vendor wants to expand their pool of options to maximize their investments across multiple products, multiple buyers, and multiple generations.

Systematically evaluating the best combinations of design options on both technical merits and business case perspectives from a large pool of IP options improves profitability and spreads risk.

### Three-part problem to solve:

1. Articulate value proposition to adopters on how the new solution is far superior to the prior ones factoring in the migration effort and risk.
2. Estimate demand, i.e., market size, that is sizable for supply side investments.
3. Each vendor on the supply side needs to prove its profitability and prioritize other competing investments.

The above needs to be solved in a low-risk, low cost, and low-friction manner for any one market opportunity. The evaluation methodology and its outcomes need to be generally agreed upon by the diverse stakeholders including potential adopters. Further this evaluation needs to be scaled to 1000’s of opportunities from which a handful will make the cut for further investigation and investment. To solve this front-end bottleneck, we need to reduce friction and lower barriers for multi-organization explorations.

This requires a **shift-left**: Shift multi-vendor evaluations as early as possible to the front-end of the design cycle. This is the planning phase, design space exploration, architecture design and power-performance, area and cost (PPAC) estimation phase for further investments.

This requires a **shift-up**: Scope it down to the architecture layer for faster interoperability testing. Abstract up the architecture implications of the lower three layers (physical, adapter/link, and protocol). Starting at the architectural layer (pre-RTL) speeds up evaluations. It allows exploring many configurations that can be synthesized (via HLS) for PPAC estimates. Simulation, emulation, and prototyping may be used for higher confidence estimates.

This requires a **shift-out**: Break out of industry silos, expand the pool of buyers and sellers, expand the pool of IP for explorations. Maximize finding (or co-developing) the best fit in terms of PPAC for the solution.

Lastly, today a lot of time is spent on repetitive and mundane activities of searching for vendors, IP, specs, tools alignment, benchmarks and test selection, PPA compatibility, etc. before the first interoperability evaluations can be started.

**AI Native**: As an industry we need to **define** **AI based automation** tools in multi-vendor environments for planning and prototyping phases. With security, governance, and safeguards in place, this virtual eco-system will include specs, proven behavioral models, curated stimuli, reference designs, interop verification methodologies, and interoperability results.

Many aspects of AI available today and in the future must be applied extensively to exponentially increase early-stage explorations while reducing mundane and repetitive activities. These include semantic and keyword search of specs, rank ordering and scoring top matches, highlighting gaps, code generation, connections to EDA tools, test benches, and benchmarks.

Incorporate best practices including encrypted models, containerized models, fast models, fixed virtual platforms, cloud, curated well-known dies and chiplets IP, local and remote verification IP, STCO, and scenario-based modeling.

Humans will set the objectives and level of interop validation required with AI automating the process flows for the design space explorations via simulations, emulation, and prototyping.

### Leaders: shape the vision

The industry needs to deliver on the advances of system-in-packages, heterogeneous integration to solve many high impact needs in scientific computing, automotive, defense and more. They can be better addressed through multi-vendor, heterogenous solutions, mixing new IP and existing designs, lower power, cost, and maximizing memory utilization (valuable commodity now).

The leaders in the industry need to start the dialog today to shape this vision, call out the challenges, and overcome hurdles for this multi-year journey.

Open chiplet economy (OCE) under Open Compute Project (OCP) is a **vendor-neutral** body encouraging participation from commercial, research labs, and academia who benefit from this initiative. OCP/OCE amplifies this effort through summits, newsletters, webinars, and more to build more visibility for this vision.

**Read** more on OCP Project to shape the vision and **Join us**:

[https://www.opencompute.org/community/open-chiplet-economy/open-framework-for-chiplet-eco-system-virtual-prototyping](https://www.opencompute.org/community/open-chiplet-economy/open-framework-for-chiplet-eco-system-virtual-prototyping)

### Related:

- [The “New Shift-Left”: Why FPGA Prototyping is the Ultimate RISC-V IP Sandbox](https://semiwiki.com/prototyping/s2c-eda/369193-the-new-shift-left-why-fpga-prototyping-is-the-ultimate-risc-v-ip-sandbox/), Daniel Nenni, Editor SemiWiki, May 2026
- “Chiplets 101: An Arteris Guide to Multi-Die Architecture”, Arteris Blog, May 2026, [https://www.arteris.com/blog/chiplets-101-an-arteris-guide-to-multi-die-architecture/](https://www.arteris.com/blog/chiplets-101-an-arteris-guide-to-multi-die-architecture/)

“The Shift-Left Approach to Software Development”, Sam Grove, MIPS, Mar 2025, [https://mips.com/blog/the-shift-left-approach-to-software-development/](https://mips.com/blog/the-shift-left-approach-to-software-development/)