---
格式版本: 2
标题: "NVIDIA Harnesses Vera CPU to Speed Up Design of Next-Generation CPUs and GPUs"
原文链接: "https://blogs.nvidia.com/blog/vera-cpu-eda/"
发布日期: "2026-07-27"
发布时间校准状态: "provisional"
发布时间需复核: "是"
发布时间来源: "fallback:scrape:provider_published_at"
发布时间证据: "provider publishedAt: 2026-07-27"
发布时间校准原因: "LLM 仲裁服务异常，按现有强证据临时采用 2026-07-27，后续需复核"
发布时间校准置信度: "medium"
发布时间候选数量: 15
发布时间严格候选数量: 4
发布时间原页读取状态: "source template page reused from URL open"
发布时间未找到原因: ""
发布时间校准时间: "2026-07-30T10:59:48+08:00"
发布时间仲裁状态: "service-error"
发布时间仲裁尝试次数: 2
发布时间仲裁耗时毫秒: 33451
发现时间: "2026-07-30T10:58:47+08:00"
入库时间: "2026-07-30T03:00:22.207Z"
来源平台: "NVIDIA Blog 搜索"
搜索渠道: "source_template"
搜索词: "https://blogs.nvidia.com/?s=bandwidth"
匹配关键词:
  - "bandwidth"
  - "roadmap"
  - "deployment"
  - "performance"
  - "latency"
  - "throughput"
相关厂家:
  - "NVIDIA"
相关专家:
  []
内容类型: "网页"
抓取工具: "Direct URL Open"
清洗工具: "Defuddle Markdown + Defuddle/Readability 正文提取"
原始附件:
  []
AI优质: "否"
AI打分: 45
AI分档: "非优质"
AI质检状态: "不通过"
AI打分理由: "文章主要介绍Vera CPU在EDA工作流中的应用，未涉及超节点/AI Rack/机柜级AI基础设施、GPU、高速互连、供电、液冷或量产落地等核心主题，仅部分提及CPU架构和带宽，与项目关注范围明显无关。"
AI质检模型: "deepseek-v4-flash"
AI质检时间: "2026-07-30T13:46:26+08:00"
AI主题相关性: 5
AI来源权威性: 15
AI新颖性: 10
AI技术细节: 5
AI商业部署信号: 0
AI完整性: 10
采集批次: "2026年7月30日10点43分13秒"
采集批次ID: "20260730-104313-925"
去重键: "https://blogs.nvidia.com/blog/vera-cpu-eda"
---

The complexity of modern chip design continues to grow as engineering teams work to develop increasingly sophisticated CPUs, GPUs and AI systems. To help meet that challenge, [NVIDIA is collaborating with industry leaders Cadence and Synopsys](https://nvidianews.nvidia.com/news/nvidia-expands-nvidia-agent-toolkit-with-nvidia-physicsnemo-and-cuda-x-libraries-to-transform-how-the-world-engineers-designs-and-builds) to optimize critical electronic design automation (EDA) applications for the NVIDIA Vera CPU.

NVIDIA is now deploying Vera across EDA workflows used to develop its next generation of CPUs and GPUs, demonstrating how high-performance CPU architecture can help accelerate some of the industry’s most demanding engineering workloads.

## Accelerating Critical EDA Workloads

What’s at stake is the pace of chip production. In turn, the tempo of industry technologies that stand to benefit from boosted EDA workloads, driving development momentum.

Simulation, verification and implementation technologies play a central role in semiconductor development. Long before a chip reaches manufacturing, engineers spend years validating behavior, identifying corner cases and refining designs through thousands of iterations.

While GPUs and AI have accelerated many aspects of chip design, several critical EDA workloads remain heavily dependent on CPU performance. Logic simulation, formal verification and portions of digital implementation often depend on fast individual cores, efficient memory systems and strong overall throughput.

That makes CPU architecture an important factor in determining how quickly engineering teams can validate designs, explore alternatives and move products toward tapeout.

![](https://blogs.nvidia.com/wp-content/uploads/2026/07/image3.jpeg)

Vera cluster in NVIDIA Portland data center.

## Highlighting Early Results With Cadence and Synopsys

NVIDIA’s initial testing includes several leading EDA applications. The results highlight Vera’s ability to accelerate two of the most compute-intensive stages of modern chip design. Early testing on selected production-class workflows shows promising results.

Cadence Jasper, a formal verification platform, uses smart proof technology and machine learning to find and fix bugs and improve verification productivity early in the design cycle.

Synopsys VCS, a high-performance functional verification solution used to simulate and validate complex chip designs before fabrication, used the same number of cores in the test.

Both applications showed up to 1.5x higher performance on selected workloads.

Beyond benchmark results, NVIDIA is working closely with both companies on application profiling, software optimization and system-level tuning designed to improve engineering productivity across a broader range of workflows over time.

## Bringing Vera to the Design Process

NVIDIA is deploying Vera throughout the EDA workflows used to create future NVIDIA processors.

Vera combines 88 custom NVIDIA Olympus CPU cores with a high-efficiency LPDDR5X memory subsystem and second generation NVIDIA Scalable Coherent Fabric designed to deliver strong per-core performance, high memory bandwidth and consistent low latency for demanding engineering applications.

These capabilities are particularly important for workloads that mix latency-sensitive jobs with large-scale regression testing across compute farms. Faster execution can shorten individual verification runs, while greater throughput enables engineers to evaluate more design alternatives and complete more validation within the same development window.

## Going From RTL to Silicon

After defining a processor’s architecture and microarchitecture, engineers describe much of its behavior at the register-transfer level (RTL). Multiple verification and implementation technologies then work together to transform that design into manufacturable silicon.

These workflows span logic simulation, formal verification, regression testing and digital implementation, helping engineers validate functionality, identify corner cases and transform designs into manufacturable silicon.

Because these stages are interconnected, improvements in verification throughput can help organizations identify issues earlier and reduce costly downstream design iterations.

## Building Future NVIDIA Chips With NVIDIA CPUs

The deployment of Vera across NVIDIA’s own engineering workflows reflects a broader strategy: accelerate each workload with the compute architecture best suited to the task.

In EDA, GPUs and AI continue to speed many algorithms, while high-performance CPUs remain essential for critical simulation, verification and implementation workloads. Together, they help improve the performance of the overall design cycle.

Looking ahead, NVIDIA plans to build on Vera with the next-generation Rosa CPU, powered by the NVIDIA Rigel core, while continuing to optimize leading EDA applications across its CPU roadmap.

By using NVIDIA CPUs to help design future NVIDIA CPUs and GPUs, the company is creating a continuous feedback loop between silicon design, software optimization and systems engineering, with each generation helping build the next.

*Learn more about NVIDIA at* [*DAC 2026*](https://www.nvidia.com/en-us/events/dac/)*.*