---
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标题: "NVIDIA GB200 NVL72: PCB & System Architecture Explained"
原文链接: "https://www.nextpcb.com/blog/nvidia-gb200-nvl72-architecture"
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发现时间: "2026-06-15T16:12:19+08:00"
入库时间: "2026-07-24T10:36:11.692Z"
来源平台: "SerpApi Google"
搜索渠道: "serpapi"
搜索词: "Compute tray"
匹配关键词:
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采集批次ID: "20260615-161212-183"
去重键: "https://www.nextpcb.com/blog/nvidia-gb200-nvl72-architecture"
---

# NVIDIA GB200 NVL72: PCB & System Architecture Explained
Posted: June, 2026 Last Updated: June, 2026 Writer: Stacy Lu

**Introduction**
When NVIDIA announced the GB200 NVL72 in March 2024, it described it as "a 72-GPU liquid-cooled rack-scale system that is essentially one giant GPU." That description is architecturally accurate in a way that has profound implications for PCB engineers and infrastructure teams: the NVL72 does not behave like a cluster of 72 individual GPUs connected by a network. It behaves like a single accelerator with 13.5 TB of unified HBM3e memory, 130 petaFLOPS of FP4 compute, and 1,800 GB/s of bidirectional interconnect bandwidth per GPU—all of it unified by a NVLink 5.0 switch fabric that fills nine dedicated switch boards within the rack. To build this system, NVIDIA pushed every dimension of PCB engineering to its current commercial limit. The NVSwitch 4.0 boards route more NVLink 5.0 differential pairs per board than any previously produced commercial PCB. The B200 GPU operates at 1,000 W per die, making air cooling physically impossible and demanding liquid cooling integration down to the board level. The 48 V DC bus distribution system carries 2,500 A of rack-level current through copper planes sized to handle that load continuously for years. And the Grace CPU–B200 GPU interconnect within each Superchip operates at 900 GB/s of coherent bandwidth—faster than the PCIe Gen5 bus that connects CPUs to GPUs in every previous server architecture. This article explains the GB200 NVL72 from the silicon outward: what the architecture achieves, how each subsystem is built, and what the system demands from the PCBs that make it function.

1. **Table of Contents**
* Introduction
* What Is the GB200 NVL72?
* The Grace Blackwell Superchip: B200 GPU + Grace CPU
* B200 GPU: Blackwell Architecture and CoWoS-L Packaging
* NVLink 5.0 Fabric: 72 GPUs as One Logical Accelerator
* NVSwitch 4.0 Boards: The Most Complex PCBs in the Rack
* Compute Trays: GB200 Superchip PCB Architecture
* Power Architecture: 120 kW at 48 V
* Liquid Cooling: Mandatory at 1,000 W per GPU
* Unified Memory Fabric: 13.5 TB HBM3e
* Networking: InfiniBand and Ethernet Scale-Out
* Performance Numbers: What GB200 NVL72 Delivers
* PCB Manufacturing Demands Across the Rack
* GB200 NVL72 vs DGX H100: System Comparison
* FAQ

* * *

## What Is the GB200 NVL72?
The GB200 NVL72 is a rack-scale AI accelerator system from NVIDIA, combining 36 GB200 Grace Blackwell Superchips (each containing one Grace ARM CPU and one B200 GPU) in a fully interconnected NVLink 5.0 fabric within a single liquid-cooled rack. At the system level, the NVL72's key specifications are:

Specification | Value
---|---
GPUs per rack | 72 B200 (from 36 GB200 Superchips)
CPUs per rack | 36 Grace (ARM Neoverse V2, 72 cores each)
GPU compute (FP4, sparse) | ~1.44 ExaFLOPS (1,440 PetaFLOPS)
GPU compute (FP8, sparse) | ~648 PetaFLOPS
GPU compute (BF16, dense) | ~162 PetaFLOPS
HBM3e memory per GPU | 192 GB
Total HBM3e (72 GPUs) | 13,824 GB (~13.5 TB)
Total CPU memory (LPDDR5X) | 36 × 480 GB = 17,280 GB (~17 TB)
Combined addressable memory | ~30 TB (HBM3e + LPDDR5X, coherent)
NVLink 5.0 bandwidth per GPU | 1,800 GB/s bidirectional
NVSwitch boards in rack | 9
Rack power consumption | ~120 kW
Cooling requirement | Mandatory direct liquid cooling (DLC)
External network | 8 × 400G InfiniBand per rack
Rack form factor | Custom NVIDIA rack (~42U equivalent)

The "NVL72" designation refers to NVLink 72—72 GPUs connected by NVLink. The predecessor DGX H100 rack connected 32 GPUs (across 4 independent nodes) and required InfiniBand to communicate between the 4 nodes; any workload requiring all 32 GPUs to exchange data simultaneously was bound by InfiniBand bandwidth between nodes. The NVL72 eliminates this constraint entirely: all 72 GPUs share a single NVLink 5.0 fabric, making the rack functionally equivalent to a single accelerator for the purposes of tensor parallelism and memory allocation.

* * *

## The Grace Blackwell Superchip: B200 GPU + Grace CPU
The GB200 (Grace Blackwell) Superchip is the fundamental computing unit of the NVL72. Each Superchip integrates one B200 GPU and one Grace CPU on a single module, connected by NVLink-C2C (Chip-to-Chip)—a 900 GB/s bidirectional, cache-coherent interconnect that operates at much higher bandwidth and lower latency than PCIe. The Grace CPU is based on 72 ARM Neoverse V2 cores fabricated on TSMC N4, designed specifically for AI server workloads. Its key characteristics for the NVL72 architecture:
* **Memory:** 480 GB LPDDR5X at 128-bit bus width, providing ~4 TB/s of CPU memory bandwidth
* **NVLink-C2C:** 900 GB/s coherent interconnect to the B200 GPU; CPU and GPU share a unified memory address space without explicit data copy operations between CPU and GPU memory
* **PCIe Gen5:** ×16 PCIe Gen5 for external connectivity (NIC, storage, management)
* **Power:** ~100 W TDP; total GB200 Superchip TDP ~1,200 W (CPU + GPU combined)

The NVLink-C2C interconnect within the Superchip replaces the PCIe host interface that connected CPUs to GPUs in every previous server architecture. PCIe Gen5 ×16 provides ~128 GB/s; NVLink-C2C provides 900 GB/s—7× higher bandwidth. More significantly, NVLink-C2C is cache-coherent: the GPU can access CPU memory (LPDDR5X) and the CPU can access GPU memory (HBM3e) without explicit data transfer or address translation overhead. This enables new AI programming models where the 30 TB combined memory (17 TB LPDDR5X + 13.5 TB HBM3e) in the rack is addressable as a single unified pool. The GB200 Superchip module is not a standard PCB add-in card. It is a multi-chip module (MCM) that mounts to the compute tray baseboard via a high-density mezzanine connector. The compute tray baseboard provides power delivery, NVLink 5.0 routing to the NVSwitch boards, PCIe Gen5 connectivity for external I/O, and liquid cooling manifold connections.

* * *

## B200 GPU: Blackwell Architecture and CoWoS-L Packaging
The B200 GPU is NVIDIA's first dual-die GPU in production. Two GB100 dies, each fabricated on TSMC's 4NP process with approximately 104 billion transistors, are joined by TSMC's CoWoS-L (Chip-on-Wafer-on-Substrate with Local silicon interconnect) advanced packaging technology. The two dies are connected across the CoWoS interposer at approximately 900 GB/s die-to-die bandwidth through a dense array of silicon microbumps. For a detailed technical treatment of CoWoS packaging and its PCB implications, see [CoWoS Packaging Explained](https://www.nextpcb.com/blog/cowos-packaging-h100-b200). From a PCB design perspective, the B200's CoWoS-L package presents as a single very large BGA component with a footprint significantly larger than the H100 SXM5 package. The B200 uses the SXM6 socket, which is physically incompatible with SXM5—an H100 baseboard cannot accept B200 GPUs without a complete baseboard redesign. The SXM6 socket has higher pin count, wider power delivery capability (for 1,000 W TDP), and supports the NVLink 5.0 interface at 200 Gb/s per lane. The B200's 8 stacks of HBM3e memory, providing 192 GB at 8.0 TB/s aggregate bandwidth, are integrated within the CoWoS package alongside the dual GB100 dies. The PCB baseboard does not route HBM signals—all HBM interconnects are within the CoWoS package substrate. However, the PCB must supply the HBM power rails (multiple VDDQ domains, each with tight ripple specifications) through the SXM6 power delivery pins.

* * *

## NVLink 5.0 Fabric: 72 GPUs as One Logical Accelerator
The NVLink 5.0 switch fabric is what transforms a collection of 72 B200 GPUs into a unified accelerator. Each B200 GPU has 18 NVLink 5.0 links, each operating at 200 Gb/s bidirectional. The total NVLink bandwidth per GPU is 18 × 200 Gb/s = 3,600 Gb/s = 1,800 GB/s bidirectional. Across 72 GPUs, the aggregate NVLink fabric bandwidth is 72 × 1,800 GB/s = approximately 130 TB/s bidirectional. This fabric is implemented through nine NVSwitch 4.0 boards, each containing multiple NVSwitch 4.0 chips. Each GPU connects to all 9 NVSwitch boards (2 NVLink links per board per GPU), creating a fully non-blocking topology: any GPU can send to any other GPU at full 1,800 GB/s simultaneously without any other GPU's traffic reducing available bandwidth. In a 72-GPU all-to-all communication (the pattern used in tensor-parallel collective operations), every GPU can simultaneously send and receive at full 1,800 GB/s. The NVSwitch 4.0 chip itself operates at 14.4 TB/s aggregate bidirectional bandwidth (72 ports × 200 GB/s per port), nearly double the 6.4 TB/s of NVSwitch 3.0 in the H100 era. For background on NVSwitch architecture and its PCB routing implications, the [NVSwitch guide](https://www.nextpcb.com/blog/what-is-nvswitch-nvidia-gpu-cluster-scale-out) provides the foundational context, and the [NVLink PCB routing guide](https://www.nextpcb.com/blog/what-is-nvlink-gpu-interconnect-pcb-routing) covers the signal integrity requirements of the NVLink 5.0 interface.

* * *

## NVSwitch 4.0 Boards: The Most Complex PCBs in the Rack
The 9 NVSwitch 4.0 boards in the GB200 NVL72 are almost certainly the most technically complex PCBs in commercial production today. Their function is straightforward to describe—switch NVLink 5.0 traffic between all 72 GPUs—but the engineering required to implement it pushes every PCB capability simultaneously. Each NVSwitch board routes NVLink 5.0 signals between:
* All 36 compute trays (each carrying 2 B200 GPUs), providing 2 NVLink 5.0 links per GPU from this switch board
* Multiple NVSwitch 4.0 chips on the board itself, which together implement the crossbar switching function

The resulting NVLink 5.0 routing density is extraordinary: a single NVSwitch board may route more than 3,000 differential pairs operating at 200 Gb/s per lane, plus power delivery for NVSwitch chips consuming approximately 400 W each. The PCB design requirements that follow from this are described in detail in the [30+ Layer HDI PCB guide](https://www.nextpcb.com/blog/why-ai-gpu-pcbs-require-30-plus-layer-hdi), but the key specifications are:
* **Layer count:** 32–40 layers, with any-layer HDI (ELIC) required to achieve the routing density beneath NVSwitch 4.0 BGA packages
* **Laminate:** Panasonic Megtron 7 (Df ~0.002 at 10 GHz) or equivalent on all NVLink 5.0 signal layers; Megtron 6 on power and ground planes
* **Copper foil:** High-VLP (HVLP, Rz < 1 μm) on all NVLink 5.0 signal layers to minimize skin-effect conductor loss at 25+ GHz
* **Impedance control:** 100 Ω ± 5% differential for all NVLink 5.0 pairs; requires LDI imaging and ± 3% dielectric thickness control
* **Via stubs:** < 5 mils (127 μm) residual stub on any through-hole via carrying NVLink 5.0 signals; any-layer HDI eliminates stubs entirely on microvia connections
* **Board dimensions:** Large format (estimated 400–600 mm per side) to accommodate connections to all 36 compute trays

These NVSwitch boards require fabricators with sequential lamination capability (4–5 press cycles for any-layer HDI), UV laser drilling systems for < 75 μm diameter microvias, precision CNC backdrilling at ± 25 μm depth accuracy, …